As a SoC Physical Design Signoff Principal Engineer, the role encompasses end-to-end ownership of SoC/Subsystem Physical Verification, ensuring alignment with defined PPA, timing, and power targets while meeting all PDK and technology requirements during Implementation. Overall, this position combines deep technical expertise, hands-on problem solving, methodology ownership, and execution leadership to ensure high-quality SoC delivery from implementation through final tapeout. Here are the key responsibilities and tasks typically associated with this role: Physical Design Sign-Off & Implementation:
Oversee physical verification of SoCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout readiness.
Own and drive physical verification and signoff methodologies, flows, automation, and execution across SoC/Block/IP levels.
Drive the final signoff process to deliver a clean, tapeout-ready database, while establishing and governing the methodologies and tools/flows required for mask generation.
Provide technical direction, estimation, planning, and execution leadership to ensure predictable project delivery and productive utilization of resources.

Technical Oversight
Provide expert guidance in resolving complex sign-off issues related to physical verification.




Work hands-on to resolve critical design, implementation, and physical verification issues, particularly those impacting project schedules and signoff quality.

Collaboration with EDA
Drive the adoption of the latest tools, technologies, and methodologies to improve sign-off efficiency and effectiveness.
Collaborate EDA tool vendors, ensuring the company’s needs are met about tool features, enhancements, and support.
Evaluate and recommend recent tools and methodologies for physical design and sign-off. Reducing TAT • Lead efforts in exploring creative approaches to physical design sign-off, driving improvements in cycle time and design quality.
Stay updated with industry trends and advancements, implementing relevant changes to maintain competitive advantage.

Quality
Ensure that all designs meet the required quality standards before sign-off, including thorough verification of timing, power, and physical integrity. Implement robust quality control measures to ensure zero-defect silicon and first-time-right success.

Compliance and Standards
Ensure compliance with industry standards and regulatory requirements during the sign-off process.

📌 Senior Principal Engineer Physical Verification Bengaluru (India)
🏢 LT-Larsen u0026 Toubro
📍 India