- Experience: 4–10 Years
- Location: Bengaluru
- Employment Type: Full-Time

About the Role

We are looking for an experienced Memory / Custom Layout Engineer to join our semiconductor design team and work on advanced SRAM, ROM, NVM and memory compiler designs.

The ideal candidate will have strong hands-on experience in full-custom memory layout, including bitcells, memory arrays, row/column decoders, sense amplifiers, I/O and peripheral circuits. The role will involve working closely with circuit design, physical verification and technology teams to develop high-quality, area-efficient and silicon-ready layouts in advanced CMOS/FinFET technologies.

Key Responsibilities

- Develop full-custom layouts for SRAM, ROM, NVM and memory compiler blocks.
- Perform hands-on layout implementation of Bitcells, Memory arrays, Row and column decoders, Sense amplifiers, I/O circuits, Peripheral circuits, Control and supporting logic
- Perform floorplanning, placement and routing for complex memory blocks.
- Develop hierarchical layouts and optimize layouts for area, performance, power and manufacturability.
- Apply advanced layout techniques for matching, symmetry, parasitic reduction and noise isolation.
- Analyze and optimize layout considering design rules, device characteristics and technology requirements.
- Perform physical verification including DRC, LVS, ERC, Antenna, EM/IR
- Debug physical verification issues and work with circuit/physical design teams to resolve them.
- Support post-layout extraction and parasitic-aware optimization.
- Work closely with circuit designers to understand layout-critical requirements and achieve desired PPA targets.
- Support block-level and top-level memory integration and tapeout activities.




- Contribute to layout methodology, automation and productivity improvements.

Required Skills & Experience

- Bachelor's or Master's degree in ECE, EE, VLSI, Microelectronics or a related field.
- Strong hands-on experience in Memory Layout / Custom Layout.
- Experience with one or more of SRAM, ROM, NVM, Memory Compiler
- Strong understanding of memory architecture and physical implementation.
- Hands-on experience with bitcell and memory array layout.
- Experience with layout of decoders, sense amplifiers, I/O and peripheral circuits.
- Strong knowledge of Floorplanning, Placement & routing, Hierarchical layout, Layout optimization, Matching, Parasitics, PPA optimization
- Experience with CMOS and/or FinFET technology nodes and advanced layout rules.
- Robust hands-on experience with DRC, LVS and physical verification.
- Experience with ERC, Antenna and EM/IR analysis.
- Proficiency in Cadence Virtuoso / Virtuoso XL.
- Experience with Calibre or equivalent physical verification tools.

Good to Have

- Experience with Memory Compiler development.
- Knowledge of memory tiling and array assembly.
- Experience with layout automation and productivity tools.
- Scripting experience using Perl/TCL/Shell
- Experience working on advanced-node memory designs, particularly FinFET technologies.
- Exposure to memory characterization, silicon bring-up or memory IP integration.

Ideal Candidate The ideal candidate is a Memory / Custom Layout Engineer with strong hands-on experience in implementing complex memory structures from schematic/netlist through layout, physical verification and tapeout.

Candidates who have worked specifically on SRAM bitcells, large memory arrays, memory compilers or advanced-node memory IPs will be strongly preferred.

📌 Memory Layout Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru