Lead Physical Design Engineer

Location: Bengaluru

Experience: 6–10 Years

Role Overview

We are looking for a Lead Physical Design Engineer with strong hands-on expertise in full-chip physical implementation. The ideal candidate will own critical aspects of the physical design flow from floorplanning through signoff, with deep expertise in Cadence Innovus and STA.

Key Responsibilities

- Drive full-chip physical design from netlist to GDS/tapeout.
- Own floorplanning, power planning, placement, CTS, routing, optimization, and signoff.
- Perform timing analysis, constraint development, timing closure, and STA debug.
- Drive setup/hold closure, congestion optimization, SI/crosstalk and PPA improvements.
- Debug and resolve DRC, LVS, antenna, IR/EM and routing issues.
- Work closely with RTL, Synthesis, STA, DFT, PD and Signoff teams to resolve design issues.
- Develop and optimize Innovus-based implementation flows and scripts.
- Support full-chip integration, block-level convergence and tapeout activities.





Core Technical Skills

- 6–10 years of hands-on Physical Design experience.
- Strong full-chip implementation and tapeout experience.
- Expert-level hands-on experience with Cadence Innovus.
- Strong expertise in STA, timing constraints and timing closure.
- Deep understanding of floorplanning, placement, CTS, routing and physical optimization.
- Experience with MMMC, SDC, ECOs, congestion, SI and PPA optimization.
- Proficiency in Tcl/Perl/Python scripting.
- Experience with advanced technology nodes and complex SoC designs is a robust plus.

Qualifications B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI or related fields.

Ideal Profile: A hands-on PD engineer who has independently driven full-chip physical implementation and timing closure through tapeout, with strong ownership of Innovus + STA.

📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru