Primary purpose of the role The role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation . The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams. This is a hands-on individual contributor role requiring solid expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging.

Major responsibilities

- RTL Design & FPGA Implementation
- Clocking, CDC & Reset Architecture
- High-Speed LVDS & Data Capture
- Timing Closure & FPGA Optimisation
- Verification & Validation
- Hardware Bring-Up & Debugging
- FPGA Configuration & Release Management
- Cross-Functional Collaboration
- Documentation & Design Governance

📌 Field-Programmable Gate Arrays Engineer (Mumbai)
🏢 Metal Power Analytical
📍 Mumbai