Position: DV Engineer - Gate Level Simulation (BB45FT RM 4354)

Key Skills

- Hands-on experience in Design Verification (DV) with Gate Level Simulation.
- Robust knowledge of SPICE, Verilog, SDF back-annotation, STA, and timing analysis.
- Experience with netlist simulation, timing libraries, timing arcs, and latch-based designs.
- Debug SDF annotation and gate-level simulation failures with root-cause analysis at gate/transistor level.
- Experience in SPICE-to-gate-level correlation and what-if analysis.
- Hands-on knowledge of SystemVerilog Assertions (SVA); UVM is a plus.
- Strong debugging, analytical, and communication skills.

Job Category: DV Engineer

Job Type: Full Time

Job Location: Hyderabad

Experience: 4-5 Years

Notice period: 0-30 days

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DV Engineer - Gate Level SimulationFT RM 4354) (Hyderabad)
🏢 Sourceright Technologies
📍 Hyderabad