- Handle block-level STA and basic timing closure
- Identify missing constraints, unconstrained paths, and clock definition issues
- Assist in setup and hold violation debug
- Generate timing reports and support signoff activities
Lead STA Engineer – 6 to 9 Years
- Own block and subsystem-level STA from early analysis to signoff
- Develop complete SDC constraints including false and multicycle paths
- Perform cross-domain and interface timing analysis
- Drive timing ECO strategies such as buffering and VT swaps
- Support low-power and multi-voltage timing scenarios