Location:

Bangalore / Hyderabad, India

Experience:

4–10 YearsEmployment Type:

Full-TimeRole SummaryWe are looking for an experienced

Analog Layout Engineer

to join our semiconductor design team and work on

high-performance analog and mixed-signal IPs

in advanced CMOS/FinFET technology nodes.The ideal candidate should have strong hands-on experience in

full-custom analog layout

, preferably with

TSMC technology nodes

, and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification.The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts.Key ResponsibilitiesDevelop

full-custom analog and mixed-signal layouts

for complex IC designs.Work on layout of analog building blocks such as:Op-AmpsBandgap referencesLDOs / RegulatorsADC/DAC blocksPLL/DLLCharge PumpsCurrent/Voltage ReferencesHigh-speed I/O and SerDes/DDR PHY circuitsImplement advanced layout techniques including:Common-centroidInterdigitationSymmetryMatchingDummy devicesGuard ringsShieldingSensitive-node isolationPerform

parasitic-aware layout optimization

and minimize the impact of routing and device parasitics on circuit performance.Work closely with analog designers to understand circuit requirements and translate schematics into optimized physical layouts.Perform

DRC, LVS, ERC and other physical verification checks

and debug layout issues.Support

PEX/post-layout simulation

and optimize layouts based on extracted parasitics.Ensure layouts meet requirements for

area, matching, noise, reliability, EM/IR and performance

.Work with advanced

TSMC technology nodes

, including FinFET-based processes.Collaborate with circuit design, verification, reliability,



and physical design teams throughout the development cycle.Support IP integration, top-level layout, tapeout activities, and design documentation.Participate in layout reviews and contribute to improving layout methodologies and productivity.Required QualificationsBachelor's or Master's degree in

Electrical/Electronics Engineering, VLSI, or related field

.4–10 years of hands-on experience in Analog/Mixed-Signal IC Layout

.Strong experience in

full-custom analog layout

.Hands-on experience with

TSMC technology nodes

is required.Experience in advanced technology nodes, preferably

16nm and below

, will be highly preferred.Solid understanding of:Analog layout fundamentalsDevice matchingParasitic effectsAnalog routing techniquesNoise isolationReliability considerationsStrong experience with

DRC/LVS/ERC and physical verification

.Experience with

PEX and post-layout simulation/debugging

.Ability to independently take blocks from

schematic → layout → verification → tapeout

.Tools & TechnologyPreferred tools:Cadence VirtuosoCadence Layout XLCalibrePVS / AssuraStarRC / Quantus or equivalent extraction toolsTechnology:TSMC CMOS / FinFET nodesPreferably

TSMC 16nm, 12nm, 7nm, 5nm and belowPreferred ExperienceCandidates with experience in layout for the following will be preferred:SerDes PHYDDR / LPDDR PHYHigh-speed I/OPLL / DLL / CDRADC / DACPower Management ICsData convertersPrecision analog blocksHigh-speed analog/mixed-signal circuitsExperience with

high-speed interface PHYs and advanced FinFET nodes

will be an added advantage.Key CompetenciesStrong analog layout fundamentalsExcellent device-matching expertiseAdvanced-node layout experienceParasitic-aware designPhysical verification/debuggingStrong schematic-to-layout understandingAbility to work independentlyGood collaboration with circuit designers and verification teamsTapeout experience

📌 Analog Layout Engineer (Mumbai)
🏢 leadIC Design
📍 Mumbai