Memory Layout design Engineers (Bengaluru)

Memory Layout design Engineers (Bengaluru)

09 Sep
|
Zia Semiconductor
|
Bengaluru

09 Sep

Zia Semiconductor

Bengaluru

Experience : 2-5 Years Experience

- Understanding of memory compiler floor plan
- Memory Leafcell layout development
- Memory backend Qualifications (DRC/LVS/ERC/DFM)
- Electrical qualifications (EM/IR)

Interested candidates can send their resumes at : [email protected]

📌 Memory Layout design Engineers (Bengaluru)
🏢 Zia Semiconductor
📍 Bengaluru

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