Mixed Signal Verification Engineer (Hyderabad)

Mixed Signal Verification Engineer (Hyderabad)

09 Sep
|
leadIC Design
|
Hyderabad

09 Sep

leadIC Design

Hyderabad

Experience: 6–10 Years
Location: Hyderabad
Employment Type: Full-Time

About the Role

We are looking for an experienced Mixed-Signal Verification / AMS Co-Simulation Engineer with robust hands-on expertise in analog-digital co-simulation, behavioral modeling, SystemVerilog/UVM-based verification, and mixed-mode simulation.
The ideal candidate will have experience verifying complex mixed-signal IPs by combining transistor-level analog simulations with digital RTL/behavioral models, developing behavioral models for analog blocks, and building automated verification environments.

You will work closely with Analog Design, Digital Design, Verification, Modeling and Physical Design teams to ensure functional correctness and robust interaction between analog and digital domains.

Key Responsibilities:

1. Mixed-Signal / AMS Co-Simulation
Perform block-level and full-chip mixed-signal simulations combining analog/SPICE solvers with digital simulation engines.
Configure and execute mixed-signal simulations using tools such as Cadence AMS Designer, Xcelium and Spectre.




Debug analog/digital interface behavior, connectivity issues, convergence problems and simulation failures.
Configure mixed-mode environments where selected blocks are simulated at transistor/schematic level while other blocks use behavioral models.
2. Analog Behavioral Modeling
Develop high-level behavioral models for analog and mixed-signal blocks using:
Verilog-AMS
Verilog
SystemVerilog
SystemVerilog RNM / wreal
Develop models that accurately represent functional and electrical behavior required for digital/mixed-signal verification.
Validate behavioral models against transistor-level schematics and simulation results.
Optimize models for simulation accuracy, performance and convergence.
3. Testbench & Verification Development
Develop reusable, metric-driven verification environments using SystemVerilog and UVM.
Build verification environments suitable for mixed-signal / UVM-AMS simulations.
Develop test s

📌 Mixed Signal Verification Engineer (Hyderabad)
🏢 leadIC Design
📍 Hyderabad

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: mixed signal verification engineer (hyderabad) / hyderabad

Subscribe to this job alert:

Get the latest job offers by email for: mixed signal verification engineer (hyderabad) / hyderabad