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SMTS Engineer to provide technical leadership and contribution on high speed Memory Controller IP Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of DDR5/6 RLD3 Memory Controller, UCIe IP designs.
The ideal candidate is one who has a proven track record on driving strategies and successful verification execution high performance IPs and/or SOC designs.
Require hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR, UCIe. Requires strong understanding of current memory controller protocols and calibration board skew and jitter modeling.
With a proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs.
Candidate is expected to be a robust team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.
Qualifications
BS w/ 12+ yrs or MS w/ 11+ yrs or PhD w/ 9+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory
📌 Functional Verification Lead (Hyderabad)
🏢 AMD
📍 Hyderabad