Full-Chip STA Signoff Engineer (Hyderabad)

Full-Chip STA Signoff Engineer (Hyderabad)

09 Sep
|
Weekday AI
|
Hyderabad

09 Sep

Weekday AI

Hyderabad

This role is for one of Weekday’s clients
Salary range: Rs 1400000 - Rs 3200000 (ie INR 14 - 32 LPA)

Min Experience: 6+ years
Location: Hyderabad
JobType: full-time
We are looking for an experienced Full-Chip STA Signoff Engineer with 6–17 years of hands-on experience in Static Timing Analysis and timing closure for complex SoC designs. The ideal candidate will have robust expertise in full-chip STA signoff, timing analysis, constraint development, timing closure, and signoff methodologies across advanced semiconductor process nodes.
You will work closely with RTL, synthesis, physical design, clock, and implementation teams to analyze timing, identify critical paths, resolve timing violations, and ensure the design meets all timing requirements before tapeout.
Key Responsibilities
Own and execute full-chip Static Timing Analysis (STA) signoff for complex SoC designs.
Perform timing analysis across multiple modes and corners (MMMC) and ensure complete timing coverage.
Analyze setup, hold, recovery, removal, minimum pulse width, clock gating, and other timing checks.
Develop,



review, and maintain timing constraints including SDC, clocks, generated clocks, input/output delays, false paths, multicycle paths, and clock uncertainty.
Debug and resolve timing violations across functional and test modes.
Perform detailed analysis of critical timing paths, identify root causes, and work with implementation teams on timing closure.
Review timing reports and distinguish between real violations, constraint issues, and tool-related exceptions.
Support timing closure through synthesis, place-and-route, ECO, and final signoff stages.
Validate timing constraints and ensure consistency between RTL, synthesis, STA, and physical implementation environments.
Analyze clock skew, latency, reconvergence, clock interactions, and clock-domain timing relationships.
Work with physical design teams to resolve congestion, buffering, routing, transition, capacitance, and timing-related issues.
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📌 Full-Chip STA Signoff Engineer (Hyderabad)
🏢 Weekday AI
📍 Hyderabad

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