Cadence Bangalore is Hiring for Analog electrical and System Validation.
About the Role
The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.
Responsibilities
Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators.
Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team)
Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL, UCIe, USB, ethernet.
Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release.
Engage in interop and Customer Debug.
Qualifications
Minimum Qualifications:
5-15 years (with Btech) or 3 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
2-3 years of management experience leading/mentoring a small team of engineers.
Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Required Skills
Experience leading System testing efforts for SERDES solutions.
Experience in PCIe/UCIe LTSSM states is a plus.
1-2 years of experience in FPGA Design and Schematic design.
1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
Familiarity with Verilog RTL coding for FPGA, python, C/C++.
Valuable communication skills.
Preferred Skills
Seasoned Systems Validation engineer who can lead SERDES projects (PCIe/CXL/UCIe) and mentor Juniors.
Pay range and compensation package
Refer to Cadence Website for more details on our SERDES IP's.
📌 Lead Analog Validation Engineer (Bengaluru)
🏢 Cadence
📍 Bengaluru
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