Job DescriptionAIML Pipeline / Dataflow Design Lead
NLocation: Bangalore, India |Company: LTSCT — L&T; Semiconductor Technologies Limited
NReporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)
NRole Summary
nWe are hiring two AIML Pipeline / Dataflow Design Leads to implement the BFOS-MPE (Broadcast-Fed Output-Stationary Matrix Processing Engine) — the compute heart of xPU. You will own the compute datapath, the broadcast network, PE array control, sparsity engines (SWS), and dual-mode (matrix + GPU) switching. You will also own the LLVM interface to the xPU.
NKey Responsibilities
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- Own micro-architecture and RTL of the BFOS-MPE compute datapath — dual 256×256 PE arrays (65,536 PEs each) operating at 2 GHz. N
- Design the broadcast-fed input network and output-stationary accumulation scheme that define the BFOS dataflow. N
- Implement PE array control, sequencing, and the sparsity engine (SWS) for structured/unstructured sparsity acceleration. N
- Architect dual-mode operation enabling switching between dense matrix (GEMM/convolution) and GPU-style workloads. N
- Drive numerical formatsand precision (FP/BF/INT, mixed precision) and validate functional correctness against reference models. N
- Coordinate and integrate contributions into the dataflow codebase and verification plan. N
- Own performance/utilization modeling, power-efficiency optimization, and PPA closure for the compute engine. N
- Own the ISA/FW routinesfor the optimal utilization of the HW compute structures in the xPU;
as part of the LLVM development. N
nRequired Skills & Experience
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- 10+ years in compute datapath, DSP, GPU, or AI-accelerator micro-architecture and RTL design. N
- Deep understanding of systolic/spatial arrays, matrix-multiply dataflows (output/weight/row-stationary), and broadcast networks. N
- Solid expertise in RTL(SystemVerilog) for high-throughput arithmetic datapaths and control. N
- Solid grounding in numerical