We are looking for an experienced Synthesis and Timing Constraints Engineer to join our ASIC/SoC Implementation team. In this role, you will lead timing constraint development and synthesis methodologies for complex SoC designs, working closely with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations across advanced technology nodes.

Key Responsibilities

- Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
- Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
- Analyze and resolve timing, area, power, and implementation challenges to achieve design targets.
- Collaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.
- Develop and enhance methodologies, flows, and automation to improve productivity and design quality.
- Support timing closure activities and drive best practices for synthesis and constraint management.
- Debug and resolve synthesis and timing-related issues during project execution.
- Contribute to flow improvements for advanced-node ASIC/SoC development. Qualifications
- Bachelors or Masters degree in Electronics Engineering or Electrical Engineering.
- 10-15 years of experience in ASIC/SoC implementation.




- Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
- Strong understanding of Static Timing Analysis (STA), timing closure, and SDC methodology.
- Hands-on scripting experience in Tcl and/or Python.
- Experience with advanced-node implementation flows.
- Solid analytical, problem-solving, and debugging skills.
- Ability to work effectively with global cross-functional teams.

Preferred Qualifications

- Experience with low-power design methodologies and optimization techniques.
- Knowledge of Physical Design and signoff flows.
- Familiarity with hierarchical and full-chip implementation methodologies.
- Successful experience supporting complex SoC tapeouts.

Why Join Us Be part of a high-performing implementation team working on next-generation semiconductor products. Youll have the opportunity to influence methodology, drive technical innovation, and contribute directly to successful tapeouts on cutting-edge process technologies.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Staff/Sr Staff Engineer, Synthesis & Timing Constraints (Bengaluru)
🏢 Renesas
📍 Bengaluru