Job Description

Role Overview:

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As an ASIC Design Engineer, you will play a key role in microarchitecture definition, RTL design, and implementation of high-speed interface IPs. You will collaborate with cross-functional teams to deliver high-performance, power-efficient, and scalable silicon solutions.

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Key Responsibilities:

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- Experience 10+yrs , Bangalore location
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- Architect and design high-performance ASIC SoCs, targeting high-speed protocols such as PCIe Gen4/5, 100G/400G Ethernet, USB3/4, SerDes-based interfaces.
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- Develop RTL using Verilog/System Verilog with a focus on performance, power, and area (PPA) optimization
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- Define and document micro-architecture and interface specifications for protocol IPs
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- Collaborate with verification teams to develop test plans, debug failures, and achieve coverage closure
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- Work closely with physical design teams on synthesis, timing closure, and floor planning support
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- Analyze and debug silicon bring-up issues related to high-speed interfaces
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- Integrate third-party IPs (SerDes, PHYs)



and ensure proper functionality and interoperability
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- Participate in design reviews and ensure adherence to design methodologies and best practices
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- Drive design quality through lint, CDC, and verification readiness checks
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Required Skills:

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- Solid experience in RTL design using Verilog/System Verilog.
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- Deep understanding of high-speed protocols , such as: PCIe (Gen4/Gen5), Ethernet (100G/400G), USB (USB3/USB4), SerDes-based architectures.
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- Solid background in microarchitecture design and trade-off analysis
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- Experience in SoC integration and subsystem design
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- Good knowledge of synthesis, STA, and physical design considerations
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Good to Have:

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- Experience in silicon bring-up and post-silicon debug
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- Exposure to advanced technology nodes and high-frequency designs
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- Scripting skills (Python/Perl/Shell) for automation
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📌 RTL Design (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru