Senior Lead Post-Silicon validation Engineer (Bengaluru)

Senior Lead Post-Silicon validation Engineer (Bengaluru)

09 Sep
|
Qualcomm
|
Bengaluru

09 Sep

Qualcomm

Bengaluru

Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
We’re looking for a hands-on validation engineer to own IP- and subsystem-level verification & validation of System MMU (SMMU) blocks within complex SoCs.
You will work across ARM-based architectures, MMU/SMMU translation flows, and the surrounding SoC infrastructure—clocks, resets, NoC/fabrics, coherency, and debug (JTAG)—to ensure functional correctness, performance, and robustness from pre-silicon through post-silicon phases.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
What You’ll Do (Key Responsibilities)




Own SMMU validation at block/IP and subsystem levels: coverage-driven test planning, stimulus development, checking/score boarding, and closure.
Develop test build reusable verification components for SMMU, including page table generators, translation fault injectors, and traffic generators.
Validate system interactions: SMMU with ARM cores, MMU/TLB, NoC/Interconnect, coherency (ACE/CHI or equivalent), and clock/reset domains (including CDC and low-power/clock-gating scenarios).
Exercise page table formats and features: stage-1/stage-2 translations, ASIDs/VMIDs, context banks/stream IDs, MSI/IOMMU operations, address translation faults, and SVA/ATS (if applicable).
Debug complex issues using JTAG and on-chip debug/trace infrastructure (ETM/STM/SWO), bring-up scripts, and logic analyzers; drive root cause with design/architecture teams.
Performance & stress validation: create stress scenarios (burst/atomic/ord

📌 Senior Lead Post-Silicon validation Engineer (Bengaluru)
🏢 Qualcomm
📍 Bengaluru

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