Experience : 3+ Years

PD candidate with PNR Tool knowledge of Innovus or FC is an absolute must with added skill of STA/Timing (PT/Tempus for STA)

Independent planning and execution of Netlist-to-GDSII.

Full exposure to all aspects of design flows like floorplanning, placement, CTS, routing, crosstalk avoidance, physical verification (DRC/LVS), PDN, Timing Closure , EOC rolling and power optimization.

Well versed with timing, PnR and PV closure, methodologies, and flow automation for better PPA and predictable convergence.

Good understanding of clocking architecture.

should have past Tapeout experience in Latest technologies.

Well versed with Tcl/Perl Scripting

Well versed of Unix command and system

Strong problem-solving skills and good communication skills.





Should have good exposure to high frequency multi voltage design convergence.

Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.

Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.

Familiarity with ASIC design flows and physical design methodologies.

Solid understanding of circuit design, device physics, and deep sub-micron technology.

Experience working on multiple technology nodes in advanced processes.

- Proficiency in automation to drive improvements in PPA.

📌 Physical Design Engineer (Bengaluru)
🏢 Mirafra Technologies
📍 Bengaluru