About the Role

We are looking for an experienced Design Verification Lead Engineer with strong expertise in PCIe and/or DDR protocols to lead verification activities for complex SoC/IP designs. The ideal candidate will have hands-on experience in developing verification environments, defining verification strategies, debugging complex issues and driving projects to successful completion.

Responsibilities

- Lead design verification activities for complex IPs, subsystems and SoCs.
- Define verification strategy, test plans, verification architecture and coverage goals.
- Develop and maintain scalable SystemVerilog/UVM-based verification environments.
- Work extensively on PCIe and/or DDR protocol verification.
- Develop test scenarios, sequences, scoreboards, monitors, assertions and functional coverage.
- Perform protocol-level verification including corner cases, error handling and stress scenarios.
- Debug complex RTL, simulation and protocol issues using waveform and simulation-debug tools.
- Drive functional, code and assertion coverage closure.
- Collaborate closely with RTL, architecture, firmware, emulation and system teams.
- Review verification plans, testbenches and verification results.
- Mentor junior and senior verification engineers and provide technical guidance.
- Track verification progress, identify risks and drive issues to closure.
- Participate in pre-silicon verification, regression, sign-off and release activities.

Qualifications





- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering or a related field.

Required Skills

- Strong hands-on experience in SystemVerilog and UVM.
- Strong understanding of digital design and RTL concepts.
- Good experience with PCIe and/or DDR protocols.
- Experience in developing and debugging UVM-based testbenches.
- Strong knowledge of functional coverage, assertions and constrained-random verification.
- Experience with simulation, regression and waveform-debug tools.
- Solid debugging and problem-solving skills.
- Experience working on complex IP, subsystem or SoC-level verification.

Preferred Skills

- PCIe
- Strong understanding of PCIe architecture and protocol layers.
- Experience with PCIe Gen3/Gen4/Gen5/Gen6 is highly desirable.
- Knowledge of LTSSM, configuration, enumeration, TLP/DLLP, flow control, error handling and link training.
- Experience verifying PCIe Root Complex / Endpoint / Switch functionality is a plus.
- - DDR
- Strong understanding of DDR4/DDR5/LPDDR protocols and architecture.
- Experience with memory controller / PHY verification.
- Knowledge of initialization, training, calibration, timing and power-management scenarios.
- Experience with protocol compliance and corner-case verification.

- Equal Opportunity Statement

Include a statement on commitment to diversity and inclusivity.

📌 Lead Design Verification (Bengaluru)
🏢 XQwave(Formerly Obsidian Solutions
📍 Bengaluru