Job DescriptionKey Responsibilities:
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- Strong experiencein CPU Core RTL Design: Single-thread / Multi-thread, In-order / Limited Out-of-Order pipelines N
- Must have completed at least one full CPU core development cycle N
- Experience in real-time/high-performance cores (e.G., ARM Cortex-R52 or equivalent) N
- Hands-on in RTL coding (Verilog/SystemVerilog), Timing analysis & closure, Power analysis & optimization N
- Positive understanding of: CPU pipeline and Performance, PPA trade-offs N
- Ability to debug and fix timing/power issues and collaborate with PD/Verification teams N