Requirement for a qualified FPGA Firmware Engineer to perform Verification activities. The engineer will work on various project requirements and provide technical support to meet critical delivery timelines and achieve project milestones.
Skillset Required:
1. Proficient in RTL verification using System Verilog (SV) and UVM
2. Awareness of FPGA design flow using VHDL as RTL language.
3. Hands on experience in developing SV/UVM verification environment.
4. Hands on experience with Questa or Modelsim or similar advanced simulation tools.
5. Hands on experience in DO-254 verification process is a plus.
6. Experience in the activities below,
- Developing tests and test environments using System Verilog UVM, for requirement-based testing.
- Developing test-plan, self-checking test-benches to meet the verification criteria and code coverage.
- Requirement validation and requirement review, Test plan Review.
- Verification setting development/update for block level and system level.
- Code coverage analysis.