ACL Digital is hiring an RTL Design Engineer (2-4 years experience) in Hyderabad with a notice period of 0-30 days
Key Responsibilities & Skills:
Core RTL Development: Experience in Verilog HDL for RTL design, microarchitecture specification writing, linting, simulation, and SoC architecture comprehension.
Timing & Implementation: Robust background in Static Timing Analysis (STA), SDC timing constraints, and working with synthesis/backend teams for physical implementation.
Tools & Scripting: Proficiency in FPGA/ASIC software toolchains (Vivado/Quartus) and scripting languages (TCL, Python, or Perl).
Interested candidates can send their resumes directly to
[email protected].
📌 Senior RTL (Hyderabad)
🏢 ACL Digital
📍 Hyderabad