Experience Level 7-18 years job Location: Bangalore/Hyderbad/Chennai
PCIe SystemC IP / Subsystem Verification
Qualification B.E / M.E / M.Tech or B.S / M.S in EE / CE
Role Objectives
- High quality silicon with no functional bugs by performing high quality pre-silicon verification
Key Responsibilities
- Develop System Verilog compliant verification environments
- Creation of verification plans and execution of coverage closure
- Provide relevant reports to show progress
- Run regressions / help set up automatic regressions
Skillset
- Proven working experience within the semiconductor industry in constraint
- random functional and formal verification
- Expertise in hardware verification using SystemVerilog/UVM. Also,
- preferably expertise in Specman E or willingness to learn on the job.
- Experience with mixed-signal IP with RNM/Verilog A model, Experience in
- C modelling for Digital Signal blocks
- Experience in MATLAB modelling is an added advantage
- Knowledge of using regression and coverage analysis tools, as well as
- knowledge of test bench qualification
- Knowledge and experience with functional safety according to ISO26262
- Working experience in international and cross-functional technical teams
- within a multi-cultural setting
- Excellent English communication skillst.
Deliverables
- Testcases ready for regression
- Qualified verification environment using SystemVerilog and SpecMan e
- Verification sign-off report fulfilling defined KPIs (e.g. 100% coverage)
- Intermediate progress / KPI status reports on agreed frequency
- Debug support to reach sign-off quality targets of IPs
- Automation for regression runs (Jenkins) Certitude closure
Tools
- Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, knowledge of
- scripting languages perl / python, automation scripts with Jenkins