Job Title: Design Verification Engineer - Gate Level Simulation (GLS) [3-8 Years]

Location: Bangalore / Hyderabad

Experience: 3-8 Years | Domain: ASIC / SoC Verification

Role Summary:

We are looking for a DV Engineer specializing in Gate Level Simulation to own GLS closure for large SoCs. You will be responsible for running Zero-delay / Unit-delay / SDF-annotated simulations, debugging timing, X-propagation, and low-power issues at gate level.

Key Responsibilities:

- Own GLS Setup and Execution for IP / Sub-system / Full SoC
- Run Zero-delay, Unit-delay, SDF-annotated simulations with VCS / Xcelium / Questa
- Generate and handle Netlist, SDF, SDC - coordinate with Synthesis and STA teams
- Debug GLS failures: Timing Violations, X-propagation, Uninitialized Flops, Clock Gating Issues, UPF related issues
- Verify Clock Gating, Reset Sequencing, Power-up Sequence at gate level
- Work on Low Power GLS - Verify Power Intent (UPF) with Power Aware Simulations
- Enable SDF Back-annotation and fix Timing vs Functional Mismatch between RTL vs Gate
- Work on Scan / MBIST / JTAG bypass modes in GLS
- Develop automation scripts for GLS flow: Netlist QC, SDF checks, Log parsing
- Collaborate with Design, STA, PD,



and DFT teams for closure

Mandatory Skills (3-8 Years):

- 3+ years of hands-on experience in GLS is MUST - Not just 1-2 times, should have done full chip GLS closure
- Solid in SystemVerilog, Verilog, UVM testbench reuse in GLS environment
- In-depth knowledge of Netlist, SDF, SDF Back-annotation, Timing Checks ($setup, $hold)
- Experience with UPF / Low Power Simulation - Isolation, Retention, Level Shifters
- Debugging skills for X's, Timing Violations, Notiming, SDF issues
- Tools: VCS, Xcelium, Verdi, Conformal, Design Compiler / Fusion Compiler flow understanding
- Scripting: Tcl, Perl, Python, Shell

Good to Have: Knowledge of DFT modes (Scan, ATPG, MBIST) Experience with STA constraints and SDC Exposure to AMS / Mixed Signal GLS is a plus

What We Don't Want:

Only RTL UVM verification without actual GLS execution. This role requires someone who has debugged real GLS failures at SoC level.

Qualification: B.E / M.Tech in ECE / VLSI

Keywords: GLS, Gate Level Simulation, SDF, Netlist Simulation, UPF, Low Power GLS, Timing Simulation, Zero Delay, X-Propagation

📌 Design Verification Engineer (Bengaluru)
🏢 Silicon Patterns
📍 Bengaluru