Bangalore / Hyderabad, India Experience: 4–10 Years
Employment Type: Full-Time
We are looking for an experienced Analog Layout Engineer to join our semiconductor design team and work on high-performance analog and mixed-signal IPs in advanced CMOS/FinFET technology nodes.
The ideal candidate should have strong hands-on experience in full-custom analog layout , preferably with TSMC technology nodes , and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification.
The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts.
Develop full-custom analog and mixed-signal layouts for complex IC designs.
Work on layout of analog building blocks such as:
Perform parasitic-aware layout optimization and minimize the impact of routing and device parasitics on circuit performance.
Ensure layouts meet requirements for area, matching, noise, reliability, EM/IR and performance .
Collaborate with circuit design, verification, reliability,



and physical design teams throughout the development cycle.
Support IP integration, top-level layout, tapeout activities, and design documentation.
Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related field .
~4–10 years of hands-on experience in Analog/Mixed-Signal IC Layout .
~ Strong experience in full-custom analog layout .
~ Hands-on experience with TSMC technology nodes is required.
~ Experience in advanced technology nodes, preferably 16nm and below , will be highly preferred.
~ Analog layout fundamentals
~ Strong experience with DRC/LVS/ERC and physical verification .
~ Experience with PEX and post-layout simulation/debugging .
~ Preferred Experience
Candidates with experience in layout for the following will be preferred:
Data converters
Experience with high-speed interface PHYs and advanced FinFET nodes will be an added advantage.
Robust analog layout fundame

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