STA Engineer (Bengaluru)

STA Engineer (Bengaluru)

09 Sep
|
Weekday AI
|
Bengaluru

09 Sep

Weekday AI

Bengaluru

This role is for one of Weekday’s clients

Min Experience: 6+ years
Location: Bengaluru
JobType: full time

We are looking for an experienced STA Engineer with 6–12 years of hands-on experience in Static Timing Analysis, synthesis, DFT, and timing closure for complex ASIC/SoC designs. The ideal candidate will have strong expertise in developing and validating timing constraints, performing MMMC-based STA, and supporting designs through implementation, signoff, and gate-level verification.

You will work closely with design, SoC, DFT, physical design, and verification teams to understand design requirements, establish timing methodologies, identify timing issues, and drive successful timing closure across functional and DFT modes.

Requirements

Key Responsibilities
- Work closely with RTL and design teams to understand design requirements, clocking architecture, timing objectives, and design constraints.
- Develop, write, and implement block-level and top-level timing constraints for synthesis and Static Timing Analysis.




- Perform comprehensive STA and timing analysis across different operating modes and process-voltage-temperature corners.
- Execute MMMC-based STA and timing closure for both functional and DFT modes.
- Analyze setup, hold, recovery, removal, clock skew, uncertainty, and other timing violations, and work with relevant teams to resolve them.
- Perform synthesis analysis and understand the impact of synthesis decisions and constraints on timing, area, and power.
- Work with DFT teams to analyze timing requirements associated with scan and test modes and ensure timing closure across DFT scenarios.
- Perform STA using industry-standard tools, preferably with hands-on experience in both Cadence Tempus and Synopsys PrimeTime.
- Generate and validate SDF (Standard Delay Format) files and support functional verification teams during Gate-Level Simulation (GLS).
- Generate and validate ETM/timing models at the IP level for accurate timing abstraction and int

📌 STA Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru

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