Job DescriptionStatic Timing Analysis (STA) Lead
NJoin the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes.
NAs a STA lead you will beworking on PrimeTime based flow development and timing closure of multi-million gate SoC design for all modes and all corners in 16/12/7/5nm processes.
NLocation: Bangalore, KA. India
NQualification and Skillset Requirements
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- Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI N
- 10+ years of practical experience in Static Timing Analysis (STA) using Primetime N
- Strong fundamentals in digital ASIC design N
- Understanding of SoC design and implementation methodology and challenges N
- Understanding of one ormore of design flows like Synthesis, Constraint development and STA (Functional and DFT modes)



and Physical Design N
- Valuable hands on expertisewith industry standard implementation tools like – Synopsys PrimeTime, Design Compiler/Fusion Compiler etc. for block as well as top level N
- Able to work with TCL and Perl scripting and flow automation N
- Excellent communicationand team work N

nRoles And Responsibilities
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- Work on STA methodology and flow development N
- Develop and integrate constraints at block and SoC level N
- Provide early feedback on design/timing issues and solutions N
- Work with Backend team for timing closure during PnR N
- Work with IP and SoC Design team in optimizing the design to meet timing N
- Work on timing closure for block/top, all modes/corners by providing timing ECOs etc. N

📌 Static Timing Analysis (Karnataka)
🏢 ScaleFlux
📍 Karnataka