Job DescriptionJob Summary
NWe are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII. The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off while working closely with RTL, synthesis, STA, DFT, and verification teams.
NKey Responsibilities
n
- N
- Execute the complete physical design flow: N
- Floorplanningn
- Power planning N
- Placementn
- Clock Tree Synthesis (CTS) N
- Routingn
- Optimization N
- ECO implementationn
- Physical sign-off N
- Perform Static Timing Analysis (STA) and resolve setup, hold, transition, and clock violations. N
- Analyze and optimize timing, power, area, congestion, and signal integrity. N
- Work on MMMC (Multi-Mode Multi-Corner) implementation and timing closure. N
- Develop and review timing constraints, including SDC, clocks, generated clocks, and timing exceptions. N
- Perform physical verification and sign-off activities including DRC, LVS, antenna, EM/IR, and power integrity checks. N




- Debug placement, routing, congestion, timing, and physical-design violations. N
- Collaborate with RTL, synthesis, STA, DFT, power, and verification teams to achieve project milestones. N
- Support tape-out activities and ensure design quality meets performance, power, area, and reliability targets. N
- Develop and improve implementation flows using Tcl/Python/Perl/Shell scripting. N
- Participate in methodology development and automation initiatives. N

nRequired TechnicalSkills
N
- n
- Robust understanding of ASIC/VLSI Physical Design flow from RTL/Netlist to GDSII. N
- Good knowledge of: N
- Floorplanningn
- Placement N
- CTSn
- Routing N
- Timing closuren
- ECO N
- Physical verification N
- Power planningn
- Strong understanding of setup/hold timing and STA. N
- Knowledge of MMMC analysis and timing constraints. N
- Experience with industry-standard EDA tools su

📌 Pd Engineer-Noida (Faridabad)
🏢 Mirafra Technologies
📍 Faridabad