Job DescriptionLTTS is looking for DV engineers with 7+ years of experience for lead role...Detailed JD is below mentioned.
N8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
N8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
NExperience in developmentof UVM based verification environments from scratch
NExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
NExperience with verification of ARM/RISC-V based CPU sub-stems or SoCs
NExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
NExperience in E tools andscripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
NExperience with revision control stems like Mercurial(Hg), Git or SVN