Job DescriptionJob Description:
N
- n
- Responsible for chip level STA convergence from early stages to signoff. N
- Participate in top level floor plan and clock planning. N
- IP & SoC timing constraints definition for all modes including DFT N
- Constraints quality check N
- Multimode-multi corner timing analysis. N
- Timing ECO generation. N
- Block and SoC level timing convergence. N
- Block and SoC level Synthesis. N
- Block and SoC level equivalence check. N

nExperience Required:
N
- n
- 5 to 8 years of experience in SOC level timing convergence N
- Synthesis and equivalence check N
- Robust timing concepts N
- Working knowledge of low power design involving multiple power domains. N
- Proficiency in scripting languages such as TCL, Perl, or Python for automation. N
- Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime N
- Exposure to complex design having multiple asynchronous clocks. N

📌 Hiring: Sta Engineer (Karnataka)
🏢 HrdWyr
📍 Karnataka