Job Description

Primary purpose of the role

n

The role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation . The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams.

n

This is a hands-on individual contributor role requiring solid expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging.

n

n

Major responsibilities:

n

1. RTL Design & FPGA Implementation

n

2. Clocking, CDC & Reset Architecture

n

3. High-Speed LVDS & Data Capture

n

4. Timing Closure & FPGA Optimisation

n

5. Verification & Validation

n

6. Hardware Bring-Up & Debugging

n

7. FPGA Configuration & Release Management

n

8. Cross-Functional Collaboration

n

9. Documentation & Design Governance

📌 Field-Programmable Gate Arrays Engineer (Mumbai)
🏢 Metal Power Analytical
📍 Mumbai