09 Sep
|
Uni Connect
|
Bengaluru
09 Sep
Uni Connect
Bengaluru
o Working experience in SOC or Subsystems designs for multiple projects o Solid understanding of DFT methodologies and experience in standard DFT tools.
Familiarity with SoC style DFT architectures including multi-clock domain and low power design practices.
Knowledge of DFT including Scan, MBIST
Knowledge of low power design methodology (static/dynamic clock gating, power gating,
energetic voltage and frequency scaling)
Valuable experience Top-level clock/reset circuit design
Knowledge on DFT simulations and debugging.
Hands On experience in ATPG/SCAN/MBIST/JTAG implementation at chip & block level.
Knowledge on Test mode timing constraint development and analysis is a plus.
Understanding of test compression and ATE debug is a plus
📌 Dft Engineer Bengaluru
🏢 Uni Connect
📍 Bengaluru