Memory Layout
Role: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories.
Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Positive problem solving and logical reasoning skills. Positive communication skills required
Experience : 3 to 7Years

The customer is looking for the following expertise:
Understanding of memory architecture
Experience in creating basic memory layouts from scratch
Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers The candidate should have over 3 years of experience with all of the above and more than 2 years of relevant industry experience overall. Additionally, they are seeking expertise in:
Knowledge of compiler issues
Understanding of reliability issues
Simulation effects
EMI (Electromagnetic Interference) considerations

📌 Memory Layout Engineer Bengaluru
🏢 UANDWE
📍 Bengaluru