09 Sep
|
SmartSoC Solutions
|
Bengaluru Urban
09 Sep
SmartSoC Solutions
Bengaluru Urban
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Minimum 4+ years of experience with a Bachelor's degree in Engineering studies or Master's degree, robust layout knowledge.
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Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
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Solid layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.
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📌 Senior Memory Layout Engineer Bengaluru Urban
🏢 SmartSoC Solutions
📍 Bengaluru Urban