Job Description

We are looking for an experienced Synthesis and Timing Constraints Engineer to join our ASIC/SoC Implementation team. In this role, you will lead timing constraint development and synthesis methodologies for complex SoC designs, working closely with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations across advanced technology nodes.

Key Responsibilities
Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
Analyze and resolve timing, area, power, and implementation challenges to achieve design targets.
Collaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.
Develop and enhance methodologies, flows, and automation to improve productivity and design quality.
Support timing closure activities and drive best practices for synthesis and constraint management.
Debug and resolve synthesis and timing-related issues during project execution.
Contribute to flow improvements for advanced-node ASIC/SoC development.

📌 Staff/senior Staff Engineer, Synthesis & Timing Constraints Bengaluru
🏢 renesas electronics
📍 Bengaluru