Job Description

We are seeking an experienced Physical Verification (PV) Engineer to drive signoff verification and tapeout readiness for advanced ASIC/SoC designs. The candidate will be responsible for executing and debugging physical verification checks, driving violation closure, maintaining foundry-qualified verification flows, and ensuring block and full-chip layouts meet manufacturing requirements before tapeout.

Key Responsibilities
Perform and drive signoff Physical Verification for block- and chip-level designs.
Execute and analyze DRC, LVS, ERC, Antenna, and Density checks using industry-standard signoff tools.
Debug verification violations and provide actionable recommendations to Physical Design and Layout teams.
Drive closure of signoff issues through effective tracking, prioritization, and cross-functional collaboration.




Maintain and support foundry-qualified rule decks, runsets, and waiver management processes.
Manage waiver tracking and ensure compliance with foundry guidelines and project signoff requirements.
Coordinate verification re-runs following design changes and ECOs to identify regressions and maintain signoff quality.
Work closely with Physical Design, Layout, Foundry/PDK, and Program teams to achieve tapeout milestones.
Generate periodic signoff status reports, metrics, and violation summaries for project reviews.
Prepare final signoff evidence including DRC/LVS-clean reports, waiver summaries, and residual risk assessments for tapeout reviews.

📌 Senior Staff Engineer, Physical Verification Bengaluru
🏢 renesas electronics
📍 Bengaluru