Job Description

We are seeking a highly motivated and experienced engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) activities for complex ASIC/SoC programs. The ideal candidate will be responsible for defining and signing off power intent (UPF/CPF), ensuring correct low-power implementation across all design stages, and driving formal equivalence verification from RTL through synthesis, DFT, implementation, and ECOs to tapeout.

This role requires close collaboration with Architecture, RTL, Verification, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness, low-power integrity, and successful tapeout execution.

Key Responsibilities

Low Power / Power Intent
Define, develop, and maintain low-power architecture and power intent using UPF/CPF.
Own power-domain and power-state specifications across IP, subsystem, and chip-level designs.
Drive implementation and integration of isolation, retention, level shifters, and power-switch methodologies.
Debug and resolve power-intent issues across RTL, synthesis, implementation, and ECO stages.




Collaborate with cross-functional teams to ensure power-aware constraints, methodologies, and signoff checks.
Drive low-power issue closure and tapeout readiness.

Formal Equivalence Verification
Execute formal equivalence checks at key design milestones:
RTL ↔ Synthesis
Synthesis ↔ DFT
DFT ↔ Physical Design
Pre-ECO ↔ Post-ECO
Analyze and debug equivalence failures related to constraints, mapping, low-power insertion, DFT logic, and ECO changes.
Drive issue resolution with explicit ownership and closure tracking.
Validate RTL, netlists, library models, constraints, and ECO patches for functional equivalence.
Generate signoff-quality reports and support milestone/tapeout reviews.

Methodology & Automation
Develop automation and reusable methodologies to improve verification efficiency and quality.
Create scripts and checks for low-power validation, equivalence verification, and issue tracking.
Drive continuous improvements in low-power and formal verification flows.

📌 Senior Staff Engineer, Low Power & Formal Equivalence Verification Vclp / Fev Bengaluru
🏢 renesas electronics
📍 Bengaluru