Job Description

We are seeking an experienced and highly motivated Principal Engineer/Manager, Design Verification to lead a team responsible for functional verification of complex digital IPs, subsystems, and SoC solutions. The ideal candidate will have deep expertise in verification methodologies, solid people leadership skills, and a proven track record of delivering high-quality silicon products on schedule.

This role requires close collaboration with architecture, design, firmware, emulation, validation, and program management teams to drive verification excellence and achieve first-silicon success.

Key Responsibilities
Own verification strategy, planning, execution, and sign-off for complex SoCs and SoC Subsystems.
Define comprehensive verification plans aligned with architectural specifications and product requirements.
Drive adoption of industry-standard verification methodologies such as UVM, SystemVerilog, Assertions, Coverage-Driven Verification, Formal Verification, and Emulation.
Establish verification metrics, coverage goals, and quality benchmarks to ensure robust product delivery.
Review verification architectures, testbench frameworks, reusable components, and coverage models.




Lead root cause analysis and resolution of critical functional issues.

Team Leadership
Build, mentor, and retain a high-performing verification team.
Manage team goals, performance reviews, career development, and succession planning.
Foster a culture of technical excellence, accountability, collaboration, and innovation.
Drive recruitment and onboarding of verification engineers across experience levels.
Partner with Design, Architecture, Validation, DFT, Firmware, and Program Management teams throughout the product lifecycle.
Track project schedules, risks, dependencies, and resource planning.
Provide regular status updates to senior leadership on project execution and quality metrics.
Ensure timely achievement of verification milestones and tape-out readiness.

Process & Quality Improvement
Define and implement best practices for verification productivity and reuse.
Drive automation initiatives to improve efficiency and reduce turnaround time.
Improve regression methodologies, debug workflows, and coverage closure processes.
Promote continuous improvement through post-silicon feedback and lessons learned.

📌 Principal Engineer/manager Design Verification Bengaluru (India)
🏢 renesas electronics
📍 India