Design Verification Engineer (Hyderabad)

Design Verification Engineer (Hyderabad)

10 Sep
|
leadIC Design
|
Hyderabad

10 Sep

leadIC Design

Hyderabad

Experience: 3+yrs
Location: Hyd/Blr

Job Overview

We are looking for a Design Verification Engineer with hands-on experience in SystemVerilog/UVM, Verilog, pre-silicon verification and Gate-Level Simulation (GLS) to work on SoC/full-chip DRAM verification.
The ideal candidate should have strong fundamentals in digital/analog circuits and CMOS concepts, along with practical experience in developing and executing verification environments, debugging failures, managing regressions and working with cross-functional teams using industry-standard EDA tools.

Key Responsibilities
Develop and execute pre-silicon verification environments for SoC/full-chip designs with focus on DRAM verification.
Develop and maintain SystemVerilog/UVM-based verification components, testbenches, sequences, tests and checkers.
Work with Verilog/SystemVerilog RTL and understand design behavior at block, subsystem and full-chip levels.
Perform Gate-Level Simulation (GLS) and analyze simulation behavior across different scenarios.
Develop and implement SystemVerilog Assertions (SVA)



to verify functional and interface-level requirements.
Execute verification regressions, analyze failures and identify root causes across RTL, testbench, assertions and simulation environments.
Debug functional and simulation issues and work closely with RTL/design teams to drive issues to closure.
Optimize regression environments to improve simulation efficiency, coverage and debug turnaround time.
Use industry-standard EDA verification tools for simulation, debug and regression execution.
Collaborate with design, architecture, verification and other cross-functional teams during the verification cycle.
Contribute to verification planning, test development, coverage analysis and overall SoC/full-chip verification sign-off.

Required Skills
Must-Have
3+ year of hands-on Design Verification experience
Robust knowledge of SystemVerilog and UVM
Good working experience with Verilog
Experience with pre-silicon verificatio

📌 Design Verification Engineer (Hyderabad)
🏢 leadIC Design
📍 Hyderabad

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