Employment Type : Full time - Permanent

Work Location : Bangalore, Chennai, Japan, Malaysia, Vietnam

Work Expertise : 5 Years - 15 Years

Desired Profile :

- Bachelor's / Master's degree in engineering from EEE / E&C; with expertise in ASIC DFT
- Define and implement DFT architecture for SoC / ASIC designs
- Perform scan insertion and scan chain stitching
- Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults
- Implement and verify MBIST / memory repair solutions
- Perform DFT rule checks (DRC) and resolve violations
- Support JTAG / boundary scan / IEEE 1149.1 implementation
Run and debug Gate Level Simulations (GLS) for DFT patterns
- Analyze and improve test coverage, pattern count, and test time
- Work closely with design, verification, physical design, and silicon validation teams
- Support post-silicon bring-up and failure analysis
- Create DFT documentation, methodology, and best-practice flows.
- Duolingo is mandatory for Japan
- Preferred immediate hires

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