We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
- You Are

You understand that verification is not about writing tests, it is about building an setting where the right bugs cannot hide, and you have the scars from finding those bugs at 2am to prove it.

Memory protocols like DDR or LPDDR do not intimidate you. Serial interfaces, complex checkers, SystemVerilog assertions that actually mean something, these are tools you reach for without thinking. You care about functional coverage because it tells you what you have not tested yet, not because it is a metric someone asked for. At Synopsys, you will work on DesignWare IP that powers real products, with a team that takes verification as seriously as you do.





What You'll Be Doing
- Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff
- Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations
- Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team
- Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
- Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time
- Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design int

📌 Asic Digital Design, Sr Staff Engineer (Telangana)
🏢 Synopsys
📍 Telangana