STA Engineer 3+ Years

Role: STA Engineer
Experience: 3+ Years
Location: Bangalore & Hyderabad

Notice Period

- 3+ Years: Immediate to 30 Days preferred
- 4+ Years: Immediate to 90 Days

Key Responsibilities

- Perform block-level and full-chip Static Timing Analysis (STA).
- Analyze and resolve Setup, Hold, Recovery, Removal, Transition and Capacitance violations.
- Work on MMMC/MCMM timing analysis across multiple modes, PVT and RC corners.
- Develop, review and validate SDC constraints and timing exceptions.
- Analyze clock latency, skew, uncertainty and critical timing paths.
- Perform timing closure and support ECO implementation.
- Work closely with Physical Design, RTL, Synthesis, CTS and DFT teams for timing convergence.
- Support pre-route and post-route timing signoff.
- Positive understanding of OCV/AOCV/POCV, CPPR/CRPR and derates.




- Develop/maintain automation scripts using Tcl/Perl/Python.

Required Skills

- 3+ years of hands-on STA experience.
- Strong knowledge of STA concepts and timing closure.
- Experience with Synopsys PrimeTime and/or Cadence Tempus.
- Strong knowledge of SDC, MMMC/MCMM and timing exceptions.
- Good understanding of CTS, clock skew, latency and uncertainty.
- Experience in timing ECOs and signoff analysis.
- Good scripting knowledge in Tcl.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, Microelectronics or related fields.

Interested Candidates

Please share your updated resume to:

[email protected]

📌 STA Engineer (Hyderabad)
🏢 Mirafra
📍 Hyderabad