Location

Bangalore / Hyderabad, India Experience:

4–10 Years Employment Type:

Full-Time Role Summary We are looking for an experienced

Analog Layout Engineer to join our semiconductor design team and work on high-performance analog and mixed-signal IPs in advanced CMOS/FinFET technology nodes. The ideal candidate should have strong hands-on experience in full-custom analog layout , preferably with

TSMC technology nodes , and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification. The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts.

Key Responsibilities Develop full-custom analog and mixed-signal layouts for complex IC designs.

Work on layout of analog building blocks such as: Op-Amps Bandgap references LDOs / Regulators ADC/DAC blocks PLL/DLL Charge Pumps Current/Voltage References High-speed I/O and SerDes/DDR PHY circuits Implement advanced layout techniques including: Common-centroid Interdigitation Symmetry Matching Dummy devices Guard rings Shielding Sensitive-node isolation Perform parasitic-aware layout optimization and minimize the impact of routing and device parasitics on circuit performance. Work closely with analog designers to understand circuit requirements and translate schematics into optimized physical layouts. Perform

DRC, LVS, ERC and other physical verification checks and debug layout issues. Support

PEX/post-layout simulation and optimize layouts based on extracted parasitics. Ensure layouts meet requirements for area, matching, noise, reliability, EM/IR and performance . Work with advanced

TSMC technology nodes , including FinFET-based processes. Collaborate with circuit design, verification, reliability, and physical design teams throughout the development cycle.



Support IP integration, top-level layout, tapeout activities, and design documentation. Participate in layout reviews and contribute to improving layout methodologies and productivity. Required Qualifications Bachelor's or Master's degree in

Electrical/Electronics Engineering, VLSI, or related field . 4–10 years of hands-on experience in Analog/Mixed-Signal IC Layout . Strong experience in full-custom analog layout . Hands-on experience with

TSMC technology nodes is required. Experience in advanced technology nodes, preferably

16nm and below , will be highly preferred. Robust understanding of: Analog layout fundamentals Device matching Parasitic effects Analog routing techniques Noise isolation Reliability considerations Strong experience with

DRC/LVS/ERC and physical verification . Experience with

PEX and post-layout simulation/debugging . Ability to independently take blocks from schematic → layout → verification → tapeout . Tools & Technology Preferred tools: Cadence Virtuoso Cadence Layout XL Calibre PVS / Assura StarRC / Quantus or equivalent extraction tools Technology: TSMC CMOS / FinFET nodes Preferably

TSMC 16nm, 12nm, 7nm, 5nm and below Preferred Experience Candidates with experience in layout for the following will be preferred: SerDes PHY DDR / LPDDR PHY High-speed I/O PLL / DLL / CDR ADC / DAC Power Management ICs Data converters Precision analog blocks High-speed analog/mixed-signal circuits Experience with high-speed interface PHYs and advanced FinFET nodes will be an added advantage.

Key Competencies

Strong analog layout fundamentals Excellent device-matching expertise Advanced-node layout experience Parasitic-aware design Physical verification/debugging Strong schematic-to-layout understanding Ability to work independently Good collaboration with circuit designers and verification teams Tapeout experience

📌 Analog Layout Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru