Job DescriptionJob Title: IO Layout Engineer
NExperience: 3+ Years
NLocation: Bangalore
NEmployment Type: Full-time
NIndustry: Semiconductors / ASIC / VLSI / IO & ESD Design
NJob Summary:
NWe are looking for a highly motivated and experienced IO Layout Engineer to join our custom layout team. The candidate will be responsible for full-custom layout of IO cells, ESD protection structures, and high-voltage interfaces for ASIC/SoC applications in deep submicron and FinFET technologies.
NKey Responsibilities:
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- Perform transistor-level custom layout of various types of IO cells including: N
- Standard IOs (CMOS, LVTTL, LVCMOS, SSTL, HSTL) N
- High-speed and specialty IOs (DDR, USB, PCIe, HDMI, etc.) N
- ESD structures, pad rings, and protection circuits N
- Work closely with IO circuit designers to interpret schematics and design intent. N
- Ensure robust layout practices for: N
- ESD compliancen
- Latch-up prevention N
- Electromigration (EM) N
- Voltage isolation and guard ring planning N
- Ensure layout meets foundry-specific DRC, LVS,



and antenna rules. N
- Run and close physical verification (DRC, LVS, ERC, ANT) using industry-standard tools. N
- Participate in floorplanning of IO ring and integration with analog/digital blocks. N
- Coordinate with packaging, ESD, and reliability teams to support silicon tapeout. N

nRequired Skills and Experience:
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- B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI. N
- 3+ years of hands-on experience in IO and/or ESD layout. N
- Robust understanding ofESD protection concepts and latch-up avoidance. N
- Expertise in Cadence Virtuoso for layout design and implementation. N
- Experience with DRC/LVStools (Calibre, Assura, PVS). N
- Familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.). N
- Good knowledge of layout-dependent effects (LDE), IR drop, and reliability constraints. N
- Attention to detail andstrong debugging/problem-solvi

📌 Hiring: Io Layout Engineer (Karnataka)
🏢 ACL Digital
📍 Karnataka