Job DescriptionJob Title: Memory Layout Engineer
NExperience: 3+yrs
NLocation: Bangalore
NJob Type: Full time
NIndustry: Semiconductors / VLSI / Memory Design
NJob Summary:
NWe are looking for a Memory Layout Engineer with robust expertise in physical layout design of memory components such as SRAM, ROM, Register Files, or custom memory IPs. The candidate will be responsible for delivering high-quality, DRC/LVS-clean layouts optimized for performance, area, and power.
NKey Responsibilities:
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Design full-custom layouts for memory components like SRAM, ROM, CAM, Register Files, or sense amplifiers. N
Work closely with circuit designers to understand schematics and translate them into optimized layouts. N
Floorplanning, transistor-level placement, routing, and matching to meet electrical and physical design constraints. N
Run physical verification (DRC, LVS, ERC, antenna checks) using industry-standard tools. N
Perform parasitic extraction (PEX) and assist in post-layout simulation. N




Ensure layouts meet design rules for process technologies (e.G., 5nm, 7nm, 16nm, 28nm). N
Implement design automation using SKILL, Python, or Tcl where applicable. N
Work with cross-functional teams (circuit, verification, CAD) to meet project milestones. N

nRequired Skills and Experience:
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B.E/B.Tech or M.E/M.Tech in Electronics or Electrical Engineering. N
3 years of hands-on experience in custom layout design, preferably in memory design. N
Solid understanding ofCMOS layout techniques, matching, shielding, and electromigration. N
Experience with: N
Tools: Cadence Virtuoso, Calibre DRC/LVS, StarRC, ICC, QRC N
Technologies: Advanced FinFET and planar nodes (28nm and below) N
Deep understanding of design rules (DRC), LVS, and physical verification sign-off flows. N
Excellent attention to detail, layout quality, and debugging skills. N

nPreferred Qualifications:
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Experience in compiler-based memory

📌 Hiring: Memory Layout Engineer Karnataka
🏢 ACL Digital
📍 Karnataka