Asic Rtl Design Engineer Bengaluru

Asic Rtl Design Engineer Bengaluru

10 Sep
|
Pqangels Technologies
|
Bengaluru

10 Sep

Pqangels Technologies

Bengaluru

RTL Design Engineer

Company: PQAngels Technologies Pvt Ltd

Experience: 5 -11 Years

Location: Bengaluru

Employment Type: Full time

About PQAngels Technologies

PQAngels Technologies is a product engineering company built across the silicon-to-software stack. Founded by experienced engineers, we help customers accelerate innovation through Semiconductor, ASIC, VLSI, Embedded, and Product Engineering services.

Job Summary

We are looking for experienced RTL Design Engineers with robust expertise in Verilog/SystemVerilog, AMBA protocols, RTL design, synthesis, lint, and CDC.

The selected candidate will be responsible for developing high-quality, synthesizable RTL, owning block-level design activities, and collaborating closely with Design Verification (DV), Physical Design (PD), and integration teams.

Key Responsibilities
Develop and implement synthesizable RTL using Verilog/SystemVerilog.
Translate microarchitecture specifications into robust RTL designs.
Take ownership of block-level design and implementation.
Perform RTL debugging and resolve design issues.
Support lint and CDC analysis and closure.
Provide synthesis support and address synthesis-related issues.
Work closely with DV and PD teams throughout the development cycle.




Support RTL integration and top-level integration activities.
Follow RTL coding standards and design guidelines.
Optimize designs for performance, area, and power.
Participate in design reviews and technical discussions.
Prepare and maintain design documentation.
Participate in customer discussions and technical meetings when required.

Mandatory Technical Skills
Strong experience in Verilog
Strong experience in SystemVerilog
Good knowledge of DDR/ PCIe /USB/ Ethernet protocols/interfaces
Hands-on experience with RTL design and microarchitecture implementation
Experience with Synthesis
Experience with Lint
Experience with CDC
Scripting knowledge in TCL / Perl / Python
Good understanding of ASIC/VLSI design flow

EDA Tools
Synopsys Design Compiler
SpyGlass
VC SpyGlass

Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, ECE, VLSI, Microelectronics, or a related field.
Relevant industry experience of 5 -11 years in RTL Design.

Soft Skills
Strong communication and interpersonal skills
Analytical and problem-solving ability
Valuable stakeholder management skills
Ability to work effectively with global teams
Strong ownership and collaboration mindset

📌 Asic Rtl Design Engineer Bengaluru
🏢 Pqangels Technologies
📍 Bengaluru

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