Key Requirements
10–12 years of experience in RTL Design and SoC Integration.
Solid hands-on experience in RTL coding using Verilog/SystemVerilog.
Experience in SoC integration of multiple IPs, subsystems and top-level modules.
Robust understanding of SoC architecture, interconnects, clock/reset architecture and IP integration.
Experience with Lint, CDC and RTL quality checks.
Hands-on experience with SDC constraints, synthesis and timing analysis.
Experience in memory optimization and memory redundancy implementation/analysis.
Experience with Formal Verification, Formality and LEC.
Experience with PowerArtist or equivalent power-analysis tools.
Valuable debugging skills for RTL, integration, CDC, synthesis and formal issues.
Experience in working with Design, Verification, DFT, PD and Architecture teams.

Key Responsibilities




Own SoC-level RTL integration of multiple IPs and subsystems.
Develop, modify and review RTL code for integration and functionality.
Perform Lint and CDC analysis, debug violations and drive closure.
Develop and maintain SDC constraints and support synthesis/timing closure.
Run and debug Synthesis, Formality and LEC flows.
Support power analysis and optimization using PowerArtist.
Resolve integration issues and ensure RTL quality and SoC readiness.

Preferred
Experience with large/complex SoC integration and multiple clock/power domains.
Knowledge of UPF/low-power design is an added advantage.
Scripting experience in Python / Tcl / Perl is preferred.

📌 Lead Engineer Rtl Integration Bengaluru (India)
🏢 Modernize Chip Solutions (MCS)
📍 India