Job Description:
Experience with STA using Primetime and PTPX required
Proficient in constraint generation.
Experience of multiple power domain implementation with complex UPF/CPF definition required
Formal verification experience (Formality/Conformal)
Perl/Tcl scripting is required
Robust problem solving and ASIC development/debugging skills.
Experience with CPU micro-architecture and their critical path.
Low power implementation techniques experience.
High speed CPU implementation.
Place and route tool experience.
Constraint management tool and Verilog coding experience