SoC Verification Engineer

Location: Bengaluru

Experience: 6–12 Years

Role Overview

We are looking for an experienced SoC Verification Engineer with robust expertise in Ethernet protocol verification, compliance validation, SerDes/controller verification, and UVM environment development.

Key Responsibilities
Develop and execute verification strategies for Ethernet-based SoC subsystems.
Drive Ethernet protocol and compliance verification across functional and corner-case scenarios.
Develop, enhance, and maintain SystemVerilog/UVM verification settings.
Verify SerDes, Ethernet controllers, MAC/PCS and related interfaces.
Develop UVM agents, sequences, scoreboards, monitors, checkers and coverage models.
Perform protocol, interoperability and compliance testing and debug failures at RTL/system level.
Drive coverage closure, regression, debug and verification signoff.
Collaborate with RTL, architecture,



firmware and validation teams to resolve complex issues.

Core Technical Skills
6–12 years of SoC/IP Design Verification experience.
Strong hands-on expertise in SystemVerilog & UVM.
Deep understanding of Ethernet protocols and compliance verification.
Experience with SerDes/controller validation.
Solid knowledge of MAC/PCS, Ethernet PHY interfaces and high-speed protocols.
Experience with constrained-random verification, assertions and functional coverage.
Strong debugging skills using simulation/waveform analysis.
Python/C/C++ scripting for verification automation is a plus.

Ideal Profile: A hands-on verification engineer capable of owning Ethernet/SerDes verification from UVM environment development through compliance testing, coverage closure and signoff.

📌 Soc Verification Engineer Bengaluru (India)
🏢 leadsoc technologies
📍 India