Role Overview

We are seeking a highly experienced Design Verification Leader to lead the
definition and execution of scalable, reusable, and high-quality verification
strategies for next-generation SoCs targeting AI, HPC, and Networking
applications. This role requires deep expertise in verifying large and complex
SoCs and a passion for building next-gen
verification platforms, leveraging automation, portability, and AI-driven
methodologies.

What You’ll Do
Define and drive the overall verification architecture for large-scale SoCs,
ensuring scalability from IP → subsystem → full SoC level
Architect and develop reusable, modular, and portable verification
platforms that can be leveraged across multiple chip programs
Establish methodologies for seamless reuse and portability,
including Portable Stimulus (PSS)-based verification flows
Lead the development of high-performance, coverage-driven testbenches using
industry-standard methodologies (e.g., UVM)
Drive multi-level verification strategies, enabling productive scaling
across:
Block-level,



Multi-block/subsystem level, Full-chip SoC level
Define and enforce verification quality metrics, coverage closure strategies,
and sign-off criteria
Champion a “fail-quick” philosophy to detect issues early and improve overall
design quality
Drive initiatives toward first-pass silicon success, minimizing escapes and
post-silicon debug effort
Leverage AI/ML techniques and AI agents to:
Automate testbench generation
Improve stimulus generation and coverage closure
Enhance regression efficiency and debug productivity
Enable intelligent verification QA and anomaly detection
Collaborate closely with design, architecture, physical design, and software
teams to ensure alignment and early issue detection
Mentor and guide DV teams on best practices, methodology adoption, and
architectural decisions

What We’re Looking For
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering,
or rela

📌 Design Verification Leader Bengaluru (India)
🏢 tylsemi
📍 India