Key Responsibilities
Own PCIe RTL design and micro-architecture for complex SoC/IP/subsystems, ensuring high performance and reliability.
Design and deliver high-quality Verilog/SystemVerilog RTL from architecture through integration and sign-off, optimizing for performance, power, and area.
Develop high-bandwidth, multi-clock, latency-sensitive designs optimized for performance, power, and area.
Work with CXL, Ethernet, and UCIe interfaces as required, ensuring seamless integration and functionality.
Drive lint, CDC/RDC, formal verification, and RTL quality to maintain high standards in design processes.
Collaborate with Architecture, DV, Physical Design, Firmware, and Emulation teams to ensure cohesive development and integration of components.
Support silicon bring-up and develop reusable IP/design components to enhance design efficiency and scalability.
Contribute to continuous improvement initiatives, providing feedback and solutions to enhance design methodologies and practices.

Overview




The Senior Staff Engineer role is pivotal in driving the design and development of cutting-edge System on Chips (SoCs) and chiplets tailored for Artificial Intelligence (AI), High-Performance Computing (HPC), and Networking applications.
Situated in the semiconductor sector, this position demands a comprehensive understanding of PCIe RTL design to produce complex, high-performance solutions.
The successful candidate will be part of a energetic team in Bangalore, contributing to next-generation technology advancements.
This role requires collaboration across architecture, physical design, firmware, and emulation teams to ensure seamless integration and delivery of superior quality products.
Candidates will be responsible for owning the PCIe RTL design and micro-architecture, ensuring that the developed systems meet the highest standards of performance, power efficiency, and area optimization.
The role demands a proactive approach to design challenges,

📌 Senior Staff Engineer Bengaluru (India)
🏢 Net Connect
📍 India